Ventana has launched its Veyron V2 RISC-V processor design that’s concentrating on information middle operators and hyperscalers in a bid to assist them design their servers with rather more precision and on a a lot sooner scale.
Shortly after launching its Veyron V1 chiplets earlier this yr, the agency has come out with a successor that may supply an IO hub and accelerators which are partnered with the UCI-Categorical chiplet connectivity normal to supply 192 cores per socket.
In a single conceptual instance, six 32-core V2 chiplets had been linked with the IO hub by means of UCI-Categorical and had been augmented with domain-specific acceleration. The IO hub might additionally join with reminiscence and parts by means of DDR5 and PCIe 5.0 controllers. Nonetheless, the agency says organizations can swap out DDR5 controllers for HBM3 controllers in the event that they so select, in line with Subsequent Platform.
Hyperscalers are taking note of Ventana
The rationale Ventana has put out its subsequent technology after launching Veyron V1 solely earlier this yr is the very fact this model used the Bunch of Wires (BoW) normal for interconnecting chiplets – which was the very best out there on the time.
However Intel then launched the UCI-Categorical normal in March final yr, which proved the superior possibility for connecting chiplets, and Ventana wasted no time in integrating this know-how into the following model of its chip know-how.
One of the promising features of this part is benchmarking, with the corporate’s figures displaying the 192-core Veyron 2 RISC-V CPU beating a number of rivals fairly simply on throughput.
These embody the 64-core Arm Neoverse V2, 56-core Intel Xeon SPR 8400+, 96-core AMD EPYC Genoa 9654, and 12-core AMD EPYC Bergamo 9754 CPUs.
The Ventana Veyron V2 processor boasted 23% extra integer all through than AMD’s Bergamo CPU, which is without doubt one of the quickest processors on the market, making this a extremely aggressive possibility for companies.
The bottom mannequin of the Veyron V2 design comes with 4 chiplets for 128 cores and eight DDR5 RAM channels, and can enter manufacturing within the third quarter of subsequent yr. It is because manufacturing is counting on the UCI-Categorical 1.1 PHY normal to turn out to be out there.
