Next gen Intel LGA1851 desktop CPU pictured

An image of an upcoming LGA1851 desktop CPU has made its method onto the web. Although an image of a CPU that is a 12 months or extra from launch is not significantly wonderful, what’s fascinating is that it seems to be a Meteor Lake pattern. Whereas Meteor Lake-S was seemingly canceled, the existence of CPUs akin to these tells us Intel obtained a great distance down the Meteor Lake-S improvement path.

The pictured CPU comes from @wxnod (through Videocardz). The CPU is certainly an LGA1851 pattern because the notches close to the sting of the chip align with schematics we have seen beforehand. What’s fascinating is the date of manufacture.

HKEPC shared the same picture however with the manufacturing date a part of the Intel FPO code unblurred. On this case, it is D234. The 234 denotes the 12 months and month of manufacture, so this CPU was manufactured in week 34 of 2022. That is just below a 12 months in the past. The D ought to check with the nation of manufacture, however I am undecided what D stands for. Probably the D1 fabs in Oregon? That is solely a guess.

HKEPC says it is a Meteor Lake-S pattern with a six P cores and eight E cores. An August 2022 manufacturing date could be too early for Arrow Lake-S, so if it is a Meteor Lake chip, It could match with the manufacturing timeline.

If Meteor Lake-S has been canceled, why are there engineering samples about? The obvious reply could be that these had been made earlier than the choice to cancel. Low yields, poor clock speeds or missed efficiency targets are all doable causes for the cancellation. The Raptor Lake refresh (itself a refresh of twelfth Gen Alder Lake) does really feel like a stopgap measure.

Maybe these chips are getting used to help motherboard producers with the design of their LGA1851 motherboards. Or possibly they’re getting used as check automobiles for the Intel 4 course of, the tile structure, or Foveros packaging.

That is lots of hypothesis from only a image of a CPU. However whereas it is one factor to scrap a chip that is on the drafting board, it is one other to scrap one which has reached the engineering pattern stage.

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