To say that the worldwide foundry market is booming proper now can be an understatement. Demand for modern course of applied sciences pushed by AI and HPC functions is unprecedented, and with Intel becoming a member of the contract chipmaking recreation, this market section is as soon as once more turning into fairly aggressive as effectively. But, that is precisely the market section that Rapidus, a foundry startup backed by the Japanese authorities and a number of other main Japanese firms, goes to enter in 2027, when its first fab comes on-line, just some years from now.
In a contemporary replace on the standing of citing the corporate’s first modern fab, Rapidus has revealed that they’re meaning to get in to the chip packaging recreation as effectively. As soon as full, the ¥5 trillion ($32 billion) fab will likely be providing each chip lithography on a 2nm node, in addition to packaging providers for chips produced inside the facility – a notable distinction in an business the place, even when packaging is not outsourced solely (OSAT), it is nonetheless usually dealt with at devoted services.
In the end, whereas the corporate needs to serve the identical purchasers as TSMC, Samsung, and Intel Foundry, the agency plans to do issues nearly fully otherwise than its rivals in a bid to hurry up chipmaking from ending design to getting a working chip out of the fab.
“We’re very happy with being Japanese,” mentioned Henri Richard, common supervisor and president of Rapidus’s subsidiary within the U.S. “[…] I do know that some individuals could also be this pondering [that] Japan is thought for high quality, consideration to element, however not essentially for pace, or flexibility. However I’ll let you know that Atsuyoshi Koike (the top of Rapidus) is a really particular government. That’s, he has all the standard of Japan, with a whole lot of American pondering. So he’s fairly a singular man, and definitely terribly targeted on creating an organization that will likely be extraordinarily versatile and very fast on its toes.”
2nm Solely, At First
Maybe probably the most vital distinction between Rapidus and conventional foundries is that the corporate will provide solely modern manufacturing applied sciences to its purchasers: 2 nm in 2027 (section 1) after which 1.4 nm sooner or later (section 2). It is a stark distinction with different contract fabs, together with Intel, which have a tendency to supply their clients a full vary of fabrication processes to land extra purchasers and produce extra chips. Apparently, Rapidus hopes that that there will likely be sufficient Japanese and American chip builders which can be inclined to make use of its 2 nm fabrication course of to provide their designs. With that mentioned, the variety of chip designers which can be utilizing probably the most superior manufacturing node at any given time is comparatively small – restricted to massive corporations who want first-mover benefit and have the margins to justify taking the danger – so it stays to be seen whether or not Rapidus’s enterprise mannequin turns into profitable. The corporate believes it would, because the market of chips made on superior nodes is rising quickly.
“Till lately IDC was giving a an estimation of the 2nm and beneath market as about $80 billion and I believe we’re going to see quickly a revision of the potential to $150 billion,” mentioned Richard. “[…] TSMC is the 800 pound gorilla within the area. Samsung is there and Intel goes to enter that area. However the market development is so vital and the demand is so excessive, that it doesn’t take a whole lot of market share for Rapidus to achieve success. One of many issues that offers me nice consolation is that once I discuss to our EDA companions, once I discuss to our potential purchasers, it’s apparent that the whole business is searching for various provide from a completely impartial foundry. There’s a place for Samsung on this business, there’s a place for Intel on this business, the business is at present owned by TSMC. However one other completely impartial foundry is greater than welcome by all the ecosystem companions and by the shoppers. So, I really feel actually, actually good about Rapidus’s positioning.”
Talking of superior course of applied sciences, it’s notable that Rapidus doesn’t plan to make use of ASML’s Excessive-NA Twinscan EXE lithography scanners for two nm manufacturing. As a substitute, Rapidus is sticking to ASML’s confirmed Low-NA scanners, which can scale back prices of Rapidus’s fab, although it would entail utilization of EUV double patterning, which brings up prices and elongates the manufacturing cycle in different methods. Even with these trade-offs, SemiAnalysis analysts imagine that given the price of Excessive-NA EUV litho instruments and halved imaging discipline, Low-NA double patterning might be extra economically viable.
“We expect we’re completely snug with the present [Low-NA EUV] resolution for 2nm, however we’d contemplate a special resolution at 1.4 nm,” mentioned Richard.
For now, solely Intel plans to make use of Excessive-NA instruments to make chips on its 14A (1.4 nm-class) fabrication course of typically in the course of the last decade. TSMC and Samsung Foundry look to be extra cautious, so Rapidus will not be alone with its perspective in direction of Excessive-NA EUV instruments.
Superior Packaging at a Main-Edge Fab
Along with superior course of applied sciences, high-end chip designers (equivalent to these used for AI and HPC functions) additionally want superior packaging applied sciences (e.g., for HBM integration) and Rapidus is able to provide them as effectively. What units the corporate other than its business friends is that it plans to construct and bundle chips in the identical fab.
“We intend to have the backend functionality in Hokkaido [semiconductor fab] as a differentiator,” Richard mentioned. “We take pleasure in ranging from scratch and have the ability to construct in all probability the primary totally built-in entrance finish again finish semiconductor fab within the business, I believe. Others will retrofit and modify their present capability, however we now have a clear sheet of paper and a part of the key sauce that Koike son is bringing to Rapidus are some very attention-grabbing concepts on learn how to combine each entrance finish and again finish amongst others.”
Intel, Samsung, and TSMC have separate services for chip manufacturing and packaging, as even probably the most subtle packaging strategies involving silicon interposers (that are basically massive chips) do not match the complexity of contemporary processors. The instruments which can be used to construct silicon interposers and tools used to make full logic chips are vastly totally different, so putting in them into the identical cleanroom usually makes little sense as they don’t complement one another very effectively.
Alternatively, transporting wafers from one website to a different is a time consuming and dangerous endeavor, so integrating every part into one campus might make sense because it significantly simplifies provide chain.
“We’re going to re reinvent the way in which, chip design, entrance finish and the again finish are working collectively towards the completion of a venture,” Richard mentioned. […] The entire thought is we are able to do it quick, with prime quality, excessive yield, and with a really brief cycle time.”
