This week Samsung Electronics and Synopsys introduced that Samsung has taped out its first cell system-on-chip on Samsung Foundry’s 3nm gate-all-around (GAA) course of know-how. The announcement, coming from digital design automation Synopsys, additional notes that Samsung used the Synopsys.ai EDA suite to place-n-route the structure and confirm design of the SoC, which in flip enabled larger efficiency.
Samsung’s unnamed high-performance cell SoC depends on ‘flagship’ general-purpose CPU and GPU architectures in addition to varied IP blocks from Synopsys. SoC designers used Synopsys.ai EDA software program, together with the Synopsys DSO.ai to fine-tune design and maximize yields in addition to Synopsys Fusion Compiler RTL-to-GDSII answer to realize larger efficiency, decrease energy, and optimize space (PPA).
And whereas the information that Samsung has developed a high-performance SoC utilizing the Synopsys.ai suite is vital, there may be one other, much more vital dimension to this announcement: which means Samsung has lastly taped out a complicated smartphone software processor on its cutting-edge 3nm GAAFET course of.
Though Samsung Foundry has been producing chips on its GAA-equipped SF3E (3 nm-class, ‘early’ node) course of for nearly two years now, Samsung Electronics has by no means used this know-how for its personal system-on-chips for smartphones or different advanced units. So far, SF3E has been used primarily for cryptocurrency mining chips, presumably because of the inevitable early teething and yield points that include being the business’s first industrial GAAFET course of.
For now, Samsung is not disclosing what particular course of node is getting used for the SoC; the official Samsung/Synposys announcement solely notes that it is for a GAA course of node. Together with their first-generation 3nm-class SF3E, Samsung Foundry has a significantly extra refined SF3 manufacturing know-how that provides quite a few enhancements over SF3E, and is due for use for mass manufacturing within the coming quarters. Given the timing of the announcement, the affordable wager is that they are utilizing SF3.
As for Samsung’s tooling partnership with Synopsys, the latter’s instruments are being credited for delivering some important efficiency enhancements to the chip’s design. Particularly, the 2 companies are crediting these instruments for enhancing the chip’s peak clockspeed by 300MHz whereas reducing down on dynamic energy utilization by 10%. To perform that, Samsung Electronics’ SoC builders used design partitioning optimization, multi-source clock tree synthesis (MSCTS), and good wire optimization to scale back sign interference, together with an easier hierarchical method. And by utilizing Synopsys Fusion Compiler, they did all this whereas with the ability to skip weeks of ‘handbook’ design work, in line with the joint press launch.
“Our longstanding collaboration has delivered modern SoC designs,” mentioned Kijoon Hong, vice chairman of SLSI at Samsung Electronics. “It is a exceptional milestone to efficiently obtain the best efficiency, energy and space on probably the most superior cell CPU cores and SoC designs in collaboration with Synopsys. Not solely have we demonstrated that AI-driven options may help us obtain PPA targets for even probably the most superior GAA course of applied sciences, however by our partnership now we have established an ultra-high-productivity design system that’s constantly delivering spectacular outcomes.”
