The stories about an inadequate provide of compute GPUs used for synthetic intelligence (AI) and high-performance computing (HPC) servers grew to become widespread in current months as demand for GPUs to energy generative AI functions exploded. TSMC admits that the largest compute GPU provide bottleneck is its chip-on-wafer-on-substrate (CoWoS) packaging capability, as it’s utilized by nearly everybody within the AI and HPC enterprise. The corporate is increasing CoWoS capability however believes that its scarcity will persist for 1.5 years.
“It will not be the scarcity of AI chips,” stated Mark Liu, the chairman of TSMC, in a dialog with Nikkei. “It is the scarcity of our CoWoS capability. […] Presently, we can not fulfill 100% of our prospects’ wants, however we attempt to assist about 80%. We predict it is a non permanent phenomenon. After our growth of [advanced chip packaging capacity], it ought to be alleviated in a single and a half years.“
TSMC presently produces the overwhelming majority of processors that energy fashionable AI providers, together with compute GPUs (akin to AMD’s Intuition MI250 and NVIDIA’s A100 and H100), FPGAs, and specialised ASICs from corporations like d-Matrix and Tenstorrent in addition to proprietary processors from cloud service suppliers, akin to AWS’s Trainium and Inferentia in addition to Google’s TPU.
It’s noteworthy that compute GPUs, FPGAs, and accelerators from CSPs all use HBM reminiscence to get the best bandwidth potential and use TSMC’s interposer-based chip-on-wafer-on-substrate packaging. Whereas conventional outsourced semiconductor meeting and check (OSAT) corporations like ASE and Amkor additionally provide related packaging applied sciences, it appears to be like like TSMC is getting the lion’s share of the orders, which is why it might barely meet demand for its packaging providers.
Trade analysts imagine that OSATs are much less motivated to supply superior packaging providers as a result of it requires them to speculate hefty quantities of capital and poses extra monetary dangers than conventional packaging. For instance, if one thing goes flawed with a mainstream processor that sits on an natural substrate, an OSAT loses just one chip, whereas if one thing goes flawed with a bundle carrying 4 chiplets and eight HBM reminiscence stacks, the corporate loses tons of if not 1000’s of {dollars}. Since OSATs don’t get substantial margins making these chiplets, such dangers decelerate the growth of superior packaging capability at OSATs, regardless that superior packaging prices considerably more cash than conventional packaging.
Similar to its trade friends, TSMC is spending billions on upcoming superior packaging services. For instance, the corporate lately introduced plans to spend almost $2.9 billion on a packaging fab that’s rumored to come back on-line in 2027.
“We’re growing our capability as rapidly as potential,” stated C.C. Wei, chief govt of TSMC, on the firm’s earnings name earlier this 12 months. “We count on these tightness considerably be launched in subsequent 12 months, most likely in the direction of the top of subsequent 12 months. […] I cannot provide the precise quantity [in terms of processed wafers capacity], however CoWoS [capacity will be doubled in 2024 vs. 2023].“
Supply: Nikkei
