As introduced final week by TSMC, later this 12 months the corporate is about to begin high-volume manufacturing on its N3P fabrication course of, and this would be the firm's most superior node for some time. Subsequent 12 months issues will get a bit extra fascinating as TSMC could have two course of applied sciences that would truly compete in opposition to one another once they enter high-volume manufacturing (HVM) within the second half of 2025.
| Marketed PPA Enhancements of New Course of Applied sciences Information introduced throughout convention calls, occasions, press briefings and press releases |
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| Compiled by AnandTech |
TSMC | ||||||||
| N3 vs N5 |
N3E vs N5 |
N3P vs N3E |
N3X vs N3P |
N2 vs N3E |
N2P vs N3E |
N2P vs N2 |
A16 vs N2P |
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| Energy | -25% -30% |
-34% | -5% -10% |
-7%*** | -25% -30% |
-30% -40% |
-5% -10% |
-15% -20% |
|
| Efficiency | +10% +15% |
+18% | +5% | +5% Fmax @1.2V** |
+10% +15% |
+15% +20% |
+5 +10% |
+8% +10% |
|
| Density* | ? | 1.3x | 1.04x | 1.10x*** | 1.15x | 1.15x | ? | 1.07x 1.10x |
|
| HVM | This autumn 2022 |
This autumn 2023 |
H2 2024 |
H2 2025 |
H2 2025 |
H2 2026 |
H2 2026 |
H2 2026 |
|
*Chip density printed by TSMC displays 'combined' chip density consisting of fifty% logic, 30% SRAM, and 20% analog.
**On the identical space.
***On the identical velocity.
The manufacturing nodes are N3X (3nm-class, excessive performance-focused) in addition to N2 (2nm-class). TSMC says that when in comparison with N3P, chips made on N3X can both decrease energy consumption by 7% on the identical frequency by decreasing Vdd from 1.0V to 0.9V, improve efficiency by 5% on the identical space, or improve transistor density by round 10% on the identical frequency. In the meantime, the important thing benefit of N3X in comparison with predecessors is its most voltage of 1.2V, which is necessary for ultra-high-performance functions, corresponding to desktop or datacenter GPUs.
TSMC's N2 will likely be TSMC's first manufacturing node to make use of gate-all-around (GAA) nanosheet transistors and this may considerably improve its efficiency, energy, and space (PPA) traits. When in comparison with N3E, semiconductors produced on N3 can minimize their energy consumption by 25% – 30% (on the identical transistor depend and frequency), improve their efficiency by 10% – 15% (on the identical transistor depend and energy), and improve transistor density by 15% (on the identical velocity and energy).
Whereas N2 will definitely be TSMC's undisputed champ on the subject of energy consumption and transistor density, N3X might probably problem it on the subject of efficiency, particularly at excessive voltages. For a lot of prospects N3X will even have a good thing about utilizing confirmed FinFET transistors, so N2 won’t be routinely the perfect of TSMC's nodes within the second half of 2025.
2026: N2P and A16
Within the following 12 months TSMC will once more provide two nodes which might be set to focus on usually related smartphone and high-performance computing functions: N2P (performance-enhanced 2nm-class) and A16 (1.6nm-class with bottom energy supply).
N2P is predicted to ship a 5% – 10% decrease energy (on the identical velocity and transistor depend) or a 5% – 10% increased efficiency (on the identical energy and transistor depend) in comparison with the unique N2. In the meantime, A16 is about to supply an as much as 20% decrease energy (on the identical velocity and transistors), as much as 10% increased efficiency (on the identical energy and transistors), and as much as 10% increased transistor density in comparison with N2P.
Preserving in thoughts that A16 options enhanced bottom energy supply community, it can possible be the node of selection for performance-minded chip designers. However after all, it will likely be dearer to make use of A16 due to the bottom energy supply, which requires extra course of steps.
